1. Field of the Invention
The present invention relates to frequency conversion apparatus and method for generating an output signal of a frequency equivalent to a coefficient multiple of a frequency of a reference clock signal, and more specifically to a frequency synthesizer capable of outputting a high accuracy clock signal (e.g., about 15 ppm) of a frequency equivalent to a coefficient multiple of the input reference clock signal used for pixel position register (or matching) of a color laser print engine.
2. Related Background Art
Although colorization of a laser print engine is strongly requested, generally a process using four-color toners of Ye, Cy, Mg and Bk requires a fourfold print time as compared with a monochrome process. Therefore, it deals with such a problem by using a print engine which uses a four-drum structure containing four photosensitive drums to be used respectively for the four colors and also uses a two-beam laser capable of performing two-line writing at once.
FIG. 1 is a schematic diagram for explaining a four-drum machine. In FIG. 1, photosensitive drums 21a to 21d each of which is dedicated for each of the four colors are disposed in line, and the respective color toners are sequentially transferred to a print sheet 29, whereby a color image is reproduced. An image writing unit shown in FIG. 2 which forms an electrostatic latent image according to a light quantity of a laser beam is provided for each photosensitive drum. Next, an operation of a laser print engine shown in FIG. 2 will be explained.
Explanation of Image Writing Unit
A laser chip 24 of two-beam type contains laser diodes a and b, and a photodiode c receiving each back light.
Driving currents Id1 and Id2 for controlling the respective laser diodes to generate beams are supplied from an LD (laser diode) driver 25. A monitor current Im from the photodiode which detected the light quantity is input to the LD driver 25, whereby APC (automatic power control) for the light quantities of the laser diodes a and b is performed. The laser chip 24 can not set an interval between two laser beam emission points to a one-pixel interval (about 42 xcexcm at 600 dpi) due to its element characteristic. For this reason, as shown in FIG. 3, with respect to a pixel area represented by lattice lines, the laser beam emission points have been obliquely arranged so that two beams are generated at the positions apart from each other by, e.g., 16 pixels along a laser scan direction.
The modulated laser beam generated from the laser chip 24 is polarized by a polygon mirror 19 fixed to a motor shaft and rotated in the direction indicated by the shown arrow, and a photosensitive drum 21 is scanned by the modulated laser beam. An f-xcex8 lens 20 is used to condense the modulated and polarized laser beams onto the photosensitive drum 21 at a constant line speed.
If predetermined electrostatic electrification has been previously performed for the photosensitive drum 21 and print toner, an adhesion quantity of the print toner changes in proportion to the irradiation light quantity on the photosensitive drum 21, whereby a halftone image can be printed. The positional relation between a BD (beam detect) mirror 22 and the photosensitive drum 21 is mechanically fixed, and the reflected laser beam from the BD mirror 22 is input to a light reception diode 23 and used to detect an information writing start position on the photosensitive drum 21. The output from the light reception diode 23 is input to a horizontal sync signal generation circuit 28, thereby generating a horizontal sync signal BD.
The horizontal sync signal BD is input to a pixel modulation circuit 26. The pixel modulation circuit 26 generates a pixel clock synchronizing with the signal BD or a clock equivalent to a coefficient multiple of the pixel clock. Based on the pixel clock, read clocks RK1 and RK2 for reading the pixel data are input to a pixel data generation unit 27. The pixel data generation unit 27 outputs pixel data D1 and D2 and corresponding writing clocks WK1 and WK2 to the pixel modulation circuit 26. Based on the input pixel data, the pixel modulation circuit 26 outputs pixel modulation signals ON1 and ON2 enabling desired laser light quantity modulation to the LD driver 25.
Correspondence of Pixel Modulation Circuit
Since a pixel modulation scale of the above-explained four-drum/two-beam laser print engine is eightfold as compared with that of a conventional one-drum/one-beam laser print engine, it is necessary to make the engine into an LSI. Further, since the four-drum machine has the image writing unit shown in FIG. 2 for each color, it is necessary to perform pixel register for at least three items as follows.
First, it is necessary to correct image position misregister (i.e., out of image position register) caused by a timing error of the signal BD in each image writing unit. This can be electrically achieved up to about {fraction (1/32)} pixel by controlling a phase (delay) of the pixel clock in the pixel modulation circuit 26.
Next, since the two-beam laser chip 24 has the low-angle oblique arrangement as described above, it is necessary to correct the pixel position because the beam interval changes, as shown in the drawings, due to error and change of the attachment angle thereof. Also, this can be electrically achieved up to about {fraction (1/32)} pixel by controlling a phase (delay) of the pixel clock based on relative pixel position setting data RP in the pixel modulation circuit 26.
Further, it is necessary to correct an error of image size caused by dispersion of optical machine accuracy occurring in equipments from the laser chip 24, the polygon mirror 19, the f-xcex8 lens 20 to the photosensitive drum 21. This can be achieved based on pixel frequency setting data DF by installing a frequency synthesizer for changing a pixel clock frequency installed in the pixel modulation circuit.
For this reason, pixel position setting data DS (i.e., a signal including the relative pixel position setting data RP, the pixel frequency setting data DF and absolute pixel position setting data RG) for pixel position register is input to the pixel modulation circuit 26 in the image writing unit of FIG. 2.
Pixel Modulation LSI Corresponding to Four-Drum/Two-Beam
FIG. 4 shows a structural example of an LSI system that the pixel modulation circuit 26 equipped with the frequency synthesizer and used for the four-drum/two-beam laser print engine (see FIG. 2) has been made into the LSI. A PLL (phase-locked loop) circuit 32 for generating a pixel clock is composed by the frequency synthesizer.
In FIG. 4, a reference clock CK is input to the PLL circuit 32 also functioning as the frequency synthesizer, and the PLL circuit 32 outputs an eight-phase clock bus K that is fourfold as compared with a pixel clock frequency and each phase is shifted by xe2x85x9 periods (i.e., shifted by {fraction (1/32)} pixel). Also, the pixel position setting data DS is input to the PLL circuit 32.
The pixel frequency setting data DF in the pixel position setting data DS is used as frequency division setting data in FIG. 5 showing a structural example of the PLL circuit 32. A control current Iv0 of a variable frequency oscillation (VCO) circuit 6 included in the PLL circuit 32 and generating an eight-phase clock is output from the PLL circuit 32. The horizontal sync signal BD is input to a BD delay circuit 30 and thus delay-controlled based on the pixel position setting data DS.
The control current Iv0 is input to the BD delay circuit 30 which includes a structure that delay circuits equivalent to the variable delay circuit used in the variable frequency oscillation circuit 6 of the PLL circuit 32 are cascaded, and the signals BD of which timings are mutually shifted by {fraction (1/32)} pixel are output from the connection points of the delay circuits.
Fine adjustment bits of the absolute pixel position setting data RG included in the pixel position setting data DS and used to set the pixel positions among the drums are used to perform the delay control to obtain the desired signal BD in the BD delay circuit 30, whereby the pixel position register among the drums can be finely adjusted up to {fraction (1/32)} pixel.
The output signal BD is input to a horizontal sync signal separation circuit 31, and thus separated into a horizontal sync signal HD1 for an antecedent laser and a horizontal sync signal HD2 for a succedent laser as shown in FIG. 6.
The horizontal sync signals HD1 and HD2 are respectively input to a sync clock generators 33a and 33b together with the eight-phase clock bus K output from the PLL circuit 32. The sync clock generators 33a and 33b generate sync clock signals SCK1 and SCK2 in synchronism with the input signals HD1 and HD2, respectively. The sync accuracy of each clock signal is {fraction (1/32)} pixel.
The sync accuracy in the one-drum/one-beam machine is enough by about xe2x85x9 pixel, however, color misregister (i.e., out of color register) in the four-drum/two-beam machine directly causes color moire and changes a color tone, and thus a request for a sync clock generator characteristic is high.
Since gradation reproduction of an image is important in case of the color laser print engine, PWM pixel modulation is generally used. Further, to flexibly cope with a digital image process, the modulation is performed by dividing a pixel (To) into 32 parts as shown in FIG. 7B.
However, the pixel data of 32 bits for one beam are huge and unachievable. For this reason, the pixel data D1 and D2 are input as six-bit data to 32-bit expansion data decoders 35a and 35b together with the corresponding writing clocks WK1 and WK2, respectively. Each of the data decoders 35a and 35b is, e.g., a 64-address/32-bit SRAM, and the data to be stored therein has been previously set to a desired value by a user.
The output 32-bit data from the data decoders 35a and 35b are subjected to serial conversion as shown in FIG. 8. For example, if it is assumed that the pixel frequency is 25 MHz (40 ns), an extremely high-accuracy signal process in which the modulation accuracy is 1.25 ns is required, and the pixel frequency shows a tendency to further increase. The sync clocks SCK1 and SCK2 and signals HRB1 and HRB2 output from the sync clock generators 33a and 33b are input to time base circuits 34a and 34b, respectively.
The time base circuit 34b includes the structure that variable delay circuits equivalent to the variable delay circuit used in the VCO circuit 6 of the PLL circuit 32 are cascaded, a pixel clock shifted from others by {fraction (1/32)} pixel is generated at each connection point, and the beam interval can be high-accurately adjusted based on the relative pixel position setting data RP in the input pixel position setting data DS. Further, in the time base circuits 34a and 34b, the upper bits of the absolute pixel position setting data RG are used for coarse adjustment in the pixel position register among the drums.
FIG. 8 shows contents of output signal buses K1 and K2 of the time base circuits 34a and 34b. 
Clocks DK0 and DK1 are used as reading timing clocks of SRAM in the data decoders 35a and 35b, respectively. The buses K0 to K3 are input to (32xe2x86x928) bit data conversion circuits 36a and 36b respectively, and then converted into eight-bit data DV shown in FIG. 19. If it is assumed that a time Td includes a time resulted in by the BD delay circuit 30 and each of the setting data RG and RP is the five-bit data, the clock delay time shown in FIG. 8 is represented by the following expressions.
Td1=Td(0)+RG(4:0)xc3x97(To/32)
Td2=Td(0)+RG(4:0)xc3x97(To/32)+RP(4:0)xc3x97(To/32)
As understood from the above expressions, the phases of the pixel data DV1 and DV2 can be controlled in the accuracy of {fraction (1/32)} pixel. If the data modulation is finally performed at this timing, desired image modulation can be achieved. The eight-bit data DV1 and DV2 of the (32xe2x86x928) bit data conversion circuits 36a and 36b are input to modulation circuits 37a and 37b together with sync clocks SK1 and SK2, respectively.
Each of the modulation circuits 37a and 37b includes a delay chain circuit that variable delay circuits equivalent to the variable delay circuit used in the VCO circuit 6 of the PLL circuit 32 are cascaded, and has the structure to generate the eight-phase clock which is controlled so that each delay quantity becomes {fraction (1/32)} pixel by DLL (delay-locked loop) control, whereby 32-bit serial modulation signals ON1A and ON2A shown in FIG. 7B can be generated.
The 32-bit serial modulation signals ON1A and ON2A are input to pulse width addition circuits 38a and 38b, respectively.
The laser diode does not emit light at once due to a luminescence principle even if a current is supplied, but emits light with delay. The laser diode stops emitting light at once if the current is interrupted.
FIGS. 9A and 9B show operations of the pulse width addition circuits 38a and 38b. When a pixel modulation driving current shown in FIG. 9A is supplied to the laser, a light emission period is reduced (narrowed) as shown in FIG. 9B. The laser does not emit light if a narrow pulse is supplied as shown at a point P2, whereby normal luminescence control can not be achieved.
To solve such the problem, if a pulse width of a predetermined period is added to each pixel modulation pulse as shown in FIG. 9C, desired light emission pulses can be obtained as shown in FIG. 9D.
The pulse width addition circuits 38a and 38b respectively include variable delay circuits equivalent to the respective variable delay circuits used in the modulation circuits 37a and 37b, and control currents Iv1 and Iv2 in the modulation circuits 37a and 37b are input to the circuits 38a and 38b respectively.
Thus, the pulse width is added by generating a coefficient current, and high-accuracy control of less than {fraction (1/100)} pixel is achieved stably.
Pixel modulation signals ON1B and ON2B output from the pulse width addition circuits 38a and 38b are input to output drivers 39a and 39b respectively, and the pixel modulation signals ON1 and ON2 are then output to the LD driver 25.
Since high accuracy of less than 1ns is required for the pulse width accuracy of the pixel modulation pulse signal, a circuit of small signal differential output type is used. The above-explained pixel modulation circuit can be achieved in an LSI process of CMOS (complementary mental-oxide semiconductor).
Conventional Frequency Synthesizer
For example, in a 600 dpi machine, since an image size error of about 16 pixels occurs in a size of about 8000 pixels, a pixel frequency control range of about xc2x10.2% (2000 ppm) is necessary. Further, high-accuracy pixel frequency control of about 15 ppm accuracy is necessary to suppress the image size error to about xe2x85x9 pixel.
FIG. 5 shows a conventional example of the frequency synthesizer.
In FIG. 5, a reference clock signal Kr of a frequency fr is input to a stationary frequency division circuit 13 of a frequency division number Nr, and then input as a reference signal R to a phase comparison circuit 15. On the other hand, an output signal Kv of a frequency fv from a variable oscillation circuit 18 of which frequency changes based on a driving control signal output from a control signal generation circuit 17 is input to a variable frequency division circuit 14, and a comparison signal V frequency-divided by a frequency division number Nv and output from the circuit 14 is then input to the phase comparison circuit 15. Here, the frequency division number Nv is variable according to the setting data DF. An up-pulse U (down-pulse D) generated when the comparison signal V delays (advances) from the reference signal R is output from the phase comparison circuit 15 and then input to a charge pump circuit 16.
An error voltage is generated based on the up-pulse U and the down-pulse D in the charge pump circuit 16 and then input to the control signal generation circuit 17, and output control is performed so that the phase of the comparison signal V matches with that of the reference signal R. The following relation is established in the above-explained frequency synthesizer.
fv=(Nv/Nr)xc3x97frxe2x80x83xe2x80x83(1)
As above, the clock signal Kv having the frequency fv equivalent to the coefficient multiple of the reference clock frequency fr can be output.
The frequency synthesizer is defined by a frequency variable range and frequency setting accuracy.
Here, the following conditions are considered.
frequency variable range: about xc2x12000 ppm
frequency setting accuracy: about 15 ppm
1/216=1/65536=15.25 ppmxe2x80x83xe2x80x83(2)
(65536)/(65536xe2x88x92128)=+1953 ppmxe2x80x83xe2x80x83(3)
(65536xe2x88x92256)/(65536xe2x88x92128)=xe2x88x921957 ppmxe2x80x83xe2x80x83(4)
From the expressions (2) to (4), the variable frequency division circuit 13 can be designed as follows by way of example, whereby the frequency synthesizer can be achieved.
the number of counter bits: 16 bits
frequency division number setting data DF: 8 bits
frequency division number range: 65280 to 65408 to 65536
However, when the frequency setting accuracy of the above-explained frequency synthesizer is increased, it is necessary to increase the frequency division number of the variable frequency division circuit. This means that a frequency check interval of the output signal Kv is increased, whereby it is necessary to structure the variable oscillation circuit 18 to be able to stably maintain the oscillation frequency during tens of thousands of clocks as in this case. Further, to stably maintain the oscillation frequency, it is necessary to stably control the oscillation output signal by not only the variable oscillation circuit 18 but also the charge pump circuit 16 using a capacitor of a large capacity unachievable by the LSI, even if attack/recovery ability is sacrificed.
However, the above-explained conventional frequency synthesizer has the following problems.
Problem 1
According to an increase of the frequency setting accuracy, the frequency stability of the variable oscillation circuit 18 becomes necessary. The variable oscillation circuit 18 capable of maintaining the frequency stability over tens of thousands of clocks could not be achieved easily in a general-purpose LSI process alone, whereby such the frequency stability could not be concretized with less cost.
Problem 2
According to the increase of the frequency setting accuracy, it is necessary to stably control the oscillation output signal by the charge pump circuit 16 using the large-capacity capacitor. For this reason, the attack/recovery ability is sacrificed, and thus a rapid output frequency change can not be performed, whereby an application range had been limited.
In consideration of the above background, an object of the present invention is to provide frequency conversion apparatus and method which can stably generate an output signal having a frequency equivalent to a coefficient multiple of a frequency of a reference clock signal, can perform a rapid output frequency change, and can be achieved with less cost.
In order to attain the above-described object according to one aspect of the present invention, there is provided a frequency conversion apparatus which generates an output signal having a frequency equivalent to a coefficient multiple of a frequency of a reference clock signal, comprising: a variable oscillation means for generating a group of clock signals having phase differences obtained by dividing substantially equally a period of the output signal; a main-phase selection means for selecting and outputting, from the group of the clock signals, a pair of the two clock signals of desired adjacent phases on the basis of a first control signal; a sub-phase selection means for selecting and outputting, from the pair of the clock signals and a clock phase within the phase difference of these signals, the one clock signal on the basis of a second control signal; an operation processing means for performing an operation process by using two frequency setting data; a logical control means for generating the first and second control signals on the basis of the clock signal selected by the sub-phase selection means, the operation result of the operation processing means, and a phase change control signal; a phase comparison means for outputting a phase difference signal representing a phase difference between the clock signal selected by the sub-phase selection means and the reference clock signal; and a control means for controlling the variable oscillation means on the basis of the phase difference signal output by the phase comparison means.
Further, according to another aspect of the present invention, there is provided a frequency conversion method which generates an output signal having a frequency equivalent to a coefficient multiple of a frequency of a reference clock signal, comprising: a variable oscillation step of generating a group of clock signals having phase differences obtained by dividing substantially equally a period of the output signal; a main-phase selection step of selecting and outputting, from the group of the clock signals, a pair of the two clock signals of desired adjacent phases on the basis of a first control signal; a sub-phase selection step of selecting and outputting, from the pair of the clock signals and a clock phase within the phase difference of these signals, the one clock signal on the basis of a second control signal; an operation processing step of performing an operation process by using two frequency setting data; a logical control step of generating the first and second control signals on the basis of the clock signal selected in the sub-phase selection step, the operation result of the operation processing step, and a phase change control signal; a phase comparison step of outputting a phase difference signal representing a phase difference between the clock signal selected in the sub-phase selection step and the reference clock signal; and a control step of controlling the clock signal generation in the variable oscillation step on the basis of the phase difference signal output in the phase comparison step.
Other objects, features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.